DIV

Unsigned Divide

$$\begin{array}{rlrl}\text{AL}& =\frac{\text{AX}}{\text{r/m8}}& \text{AH}& =\text{AX}\mathrm{mod}\text{r/m8}\\ \text{AX}& =\frac{\text{DX:AX}}{\text{r/m16}}& \text{DX}& =\text{DX:AX}\mathrm{mod}\text{r/m16}\\ \text{EAX}& =\frac{\text{EDX:EAX}}{\text{r/m32}}& \text{EDX}& =\text{EDX:EAX}\mathrm{mod}\text{r/m32}\\ \text{RAX}& =\frac{\text{RDX:RAX}}{\text{r/m64}}& \text{RDX}& =\text{RDX:RAX}\mathrm{mod}\text{r/m64}\end{array}$$

Description

Divides unsigned the value in the AX, DX:AX, EDX:EAX, or RDX:RAX registers (dividend) by the source operand (divisor) and stores the result in the AX (AH:AL), DX:AX, EDX:EAX, or RDX:RAX registers. The source operand can be a general-purpose register or a memory location. The action of this instruction depends on the operand size (dividend/divisor). Division using 64-bit operand is available only in 64-bit mode.

Non-integral results are truncated (chopped) towards 0. The remainder is always less than the divisor in magnitude. Overflow is indicated with the #DE (divide error) exception rather than with the CF flag.

In 64-bit mode, the instruction’s default operation size is 32 bits. Use of the REX.R prefix permits access to additional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. In 64-bit mode when REX.W is applied, the instruction divides the unsigned value in RDX:RAX by the source operand and stores the quotient in RAX, the remainder in RDX.

See the summary chart at the beginning of this section for encoding data and limits. See the table below.

Operation

SRC: operand

OperandSize = 8

if SRC == 0 {
    DE; // divide error
}

temp = AX / SRC;
if temp > 0xFF {
    DE; // divide error
} else {
    AL = temp;
    AH = AX % SRC;
}

OperandSize = 16

if SRC == 0 {
    DE; // divide error
}

temp = DX:AX / SRC;
if temp > 0xFFFF {
    DE; // divide error
} else {
    AX = temp;
    DX = DX:AX % SRC;
}

OperandSize = 32

if SRC == 0 {
    DE; // divide error
}

temp = EDX:EAX / SRC;
if temp > 0xFFFF_FFFF {
    DE; // divide error
} else {
    EAX = temp;
    EDX = EDX:EAX % SRC;
}

OperandSize = 64

if SRC == 0 {
    DE; // divide error
}

temp = RDX:RAX / SRC;
if temp > 0xFFFF_FFFF_FFFF_FFFF {
    DE; // divide error
} else {
    RAX = temp;
    RDX = RDX:RAX % SRC;
}

Flags Affected

The CF, OF, SF, ZF, AF, and PF flags are undefined.